This invention relates to a filter arrangement comprising at least a first resistor and a first capacitor, which provide a time constant determined by the product of the resistance of the resistor and the capacitance of the capacitor, and a trimming circuit comprising a switched second capacitor for adjusting the time constant of the filler arrangement.
By means of such an arrangement any known active or passive filter can be formed. In particular, such an arrangement may constitute an input or an output filter in a discrete-time switched-capacitor filter.
In integrated circuits resistors and capacitors can be fabricated only with a limited accuracy. As a result the time constants in the filter arrangements are very inaccurate. The article "Switched Resistor Filters--A continuous Time Approach to Monolithic MOS-Filter Design", IEEE Transactions on Circuits and Systems, Vol. Cas-29, No. 5, May 1982, pages 306-315, describes a filter arrangement which enables more acurate time constants to be obtained. In this arrangement each resistor is constituted by a field-effect transistor (FET) whose resistance is determined by a voltage established between the gate and the source by means of a capacitor. For each resistor there are provided two FETs which are alternately switched into the actual filter and into a trimming circuit. In this trimming circuit the resistance of the FET is made equal to the equivalent resistance of a switched capacitor. This results in a time constant which only depends on the ratio between the capacitance of the capacitor in the actual filter and the capacitance of the switched capacitor and the clock frequency with which the capacitor is switched. During integration a very accurate capacitance ratio between the capacitors can be obtained. The clock frequency, which is determined by an external circuit, can also be defined accurately.
However, a drawback of this known circuit arrangement is that the non-linear relationship between the resistance of the FETs and the control voltages gives rise to inaccuracies in the time constants. Moreover the resistances of the FETs for equal gate voltages are found to differ substantially due to differences in the voltages on the drain electrodes and on the backgates. Further, the use of two FETs for each resistor is likely to give rise to crosstalk between the clock signals employed for switching.